(1) Field of the Invention
The present invention relates to a program conversion apparatus and a program conversion method, and in particular to a technique for generating a program by selectively using a plurality of instruction sets.
(2) Description of the Related Art
Processors that have been conventionally commercialized select one of a plurality of instruction sets dynamically, by executing a particular branch instruction, and interpret and execute machine instructions according to the selected instruction set.
As one example of such, there is a processor that dynamically selects one of an HD (High-Density) instruction set and an HS (High-Speed) instruction set, and operates according to the selected instruction set. An HD instruction set is composed of machine instructions that can be aligned on the byte boundary. An HS instruction set is composed of machine instructions that can be aligned only on the word boundary.
Due to the different alignment boundary, an HS instruction occupies a larger code size than an equivalent HD instruction, whereas an HS instruction is executed at higher speed than an equivalent HD instruction.
Taking advantage of such characteristics of both the instructions, a program can be generated by using an HS instruction for a program part that occupies relatively a small code size with respect to the entire program and that is executed with high frequency, and using an HD instruction for the other program part, and can be executed by the processor. By doing so, the program size can be prevented from increasing, and the execution time can be shortened.
FIGS. 15A and 15B show examples of source programs described by taking advantage of such characteristics of the instructions. These source programs are described in C language. A pragma directive “#pragma_func_mode_XX (XX is HD or HS)” described in each of these source programs directs a compiler according to a conventional technique to compile the source program described to follow this directive into a machine instruction sequence that belongs to an XX (XX is HD or HS) instruction set. It is assumed here that such a pragma directive is provided for every function. Based on the pragma directive, a function “f” is compiled into an HD instruction sequence, and a function “g” is compiled into an HS instruction sequence.
Hereafter, the processor that is in a state where an HD instruction is being selected is referred to as the processor being in an operation mode of an “HD mode”, and the processor that is in a state where an HS instruction is being selected is referred to as the processor being in an operation mode of an “HS mode”. Also, a function that is to be compiled into an HD instruction sequence is referred to as an “HD function”, and a function that is to be compiled into an HS instruction sequence is referred to as an “HS function”. The particular branch instruction mentioned above is an instruction for causing a branch with mode change, and is hereafter referred to a “branch-with-mode-change instruction”.
FIG. 16 shows examples of branch instructions. An “instruction” field 351 stores a mnemonic that represents a branch instruction, an “operand” field 352 stores an operand that can be included in the branch instruction, and a “feature” field 353 stores a feature of the branch instruction. These branch instructions can be included in an HD instruction set and in an HS instruction set.
As shown in the “feature” field 353, the operation mode of the processor (i.e., the instruction set currently selected by the processor) is changed when “brc”, “jmpc”, “callc”, and “ret” instructions are executed. The operation mode of the processor is maintained when “jmp”, and “call” instructions are executed.
FIGS. 17A and 17B show assembler programs that the conventional compiler generates for the source programs shown in FIGS. 15A and 15B. As is well known, the conventional compiler generates, in addition to machine instruction sequences represented by the assembler programs, symbol information (not shown) about a label that allows external reference.
The following is a supplemental explanation on the assembly program shown in FIG. 17A. The conventional compiler judges, for a function call “g( );” and a function call “func=&g; (*func) ( );” described in the function “f” shown in FIG. 15A, whether an instruction set of the caller function “f” and an instruction set of the callee function “g” are the same or not, based on the pragma directive described in each of the source programs. Then, the compiler judges that the instruction sets are not the same, and compiles the function call “g( );” into an instruction for a subroutine call with mode change “callc—0g” that is for causing a branch using direct addressing and for changing the operation mode of the processor, and compiles the function call “func=&g; (*func) ( );” into an instruction for a subroutine call with mode change “callc R0” that is for causing a branch using indirect addressing and for changing the operation mode of the processor. Hereafter, an instruction for a subroutine call with mode change is referred to as a “mode-changing subroutine call instruction”.
On the other hand, if judging that the instruction set of the caller function and the instruction set of the callee function are the same, the compiler compiles each of those function calls into an instruction for a subroutine call instruction “call” that maintains the operation mode of the processor.
A linkage editor (or simply a “linker”) according to a conventional technique links the object programs shown in FIGS. 17A and 17B, to generate an executable program (not shown) that is executable by the processor.
In this way, a compiler conventionally judges whether to generate a subroutine call instruction for maintaining the operation mode or a mode-changing subroutine call instruction for changing the operation mode. According to the judgment result, the compiler selectively generates one of a “call” instruction and a “callc” instruction.
However, as one disadvantage, a compiler and a linker according to the conventional technique cannot judge which one of a “call” instruction and a “callc” instruction is to be generated for a function call, until an instruction set of its caller function and an instruction set of its callee function are definite, and accordingly, cannot compile the function call until then.
Also, as another disadvantage, when a source program. including a callee function is recompiled and consequently an instruction set of the callee function is changed, a “call” instruction that has already been generated for a function call to call the callee function needs to be changed to a “callc” instruction, and vice versa. This means that a source program that includes the function call procedure also needs to be recompiled.
The first problem therefore is that software development efficiency may be degraded by the disadvantages explained above.
Further, for a branch instruction using indirect addressing, its branch destination may differ every time when the branch is executed. The second problem therefore is that a subroutine call instruction using indirect addressing inherently may not function correctly, regardless of whether a “call” instruction or a “callc” instruction is generated.
These problems are not limited to such a function call as explained above, but may also occur in a typical branch to a label that allows external reference.